1. Field of the Disclosure
Generally, the present disclosure relates to the fabrication of sophisticated integrated circuits including highly scaled transistor elements comprising gate structures of increased capacitance, including a high-k gate dielectric of increased permittivity compared to conventional gate dielectrics, such as silicon dioxide and silicon nitride.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit elements that substantially determine performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity and increase of gate resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are based on silicon, due to its substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the dominant importance of silicon in fabricating semiconductor devices, has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, during anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, silicon dioxide is preferably used as a gate insulation layer in field effect transistors that separates the gate electrode, frequently comprised of polysilicon or other metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has continuously been decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although, generally, high speed transistor elements having an extremely short channel may preferably be used for high speed applications, whereas transistor elements with a longer channel may be used for less critical applications, such as storage transistor elements, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range or 1-2 nm that may not be compatible with requirements for performance driven circuits.
Therefore, replacing silicon dioxide as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide gate layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. Commonly, a thickness required for achieving a specified capacitive coupling with silicon dioxide is referred to as capacitance equivalent thickness (CET). Thus, at a first glance, it appears that simply replacing the silicon dioxide with high-k materials is a straightforward way to obtain a capacitance equivalent thickness in the range of 1 nm and less.
It has thus been suggested to replace silicon dioxide with high permittivity materials such as tantalum oxide (Ta2O5) with a k of approximately 25, strontium titanium oxide (SrTiO3) having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
Additionally, transistor performance may be increased by providing an appropriate conductive material for the gate electrode to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance based on the same thickness as a silicon dioxide layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, the non-polysilicon material, such as titanium nitride and the like, may be formed to connect to the high dielectric material, thereby substantially avoiding the presence of a depletion zone. Since, typically, a low threshold voltage of the transistor, which represents the voltage at which a conductive channel forms in the channel region, is desired to obtain high drive currents, commonly, the controllability of the respective channel requires pronounced lateral dopant profiles and dopant gradients, at least in the vicinity of the PN junctions. Therefore, so-called halo regions are usually formed by ion implantation in order to introduce a dopant species whose conductivity type corresponds to the conductivity type of the remaining channel and semiconductor region so as to “reinforce” the resulting PN junction dopant gradient after the formation of respective extension and deep drain and source regions. In this way, the threshold voltage of the transistor significantly determines the controllability of the channel, wherein a significant variance of the threshold voltage may be observed for reduced gate lengths. Hence, by providing an appropriate halo implantation region, the controllability of the channel may be enhanced, thereby also reducing the variance of the threshold voltage, which is also referred to as threshold roll off, and also reducing significant variations of transistor performance with a variation in gate length. Since the threshold voltage of the transistors is significantly determined by the work function of the metal-containing gate material, an appropriate adjustment of the effective work function with respect to the conductivity type of the transistor under consideration has to be guaranteed.
In addition to increasing the capacitive coupling of the gate electrodes to the channel region and the overall reduction of the gate resistance, further techniques have been developed in an attempt to further enhance performance of silicon-based field effect transistors. One promising approach is the modification of the lattice structure of a silicon crystal, since, by appropriately generating strain in the channel region of the transistors, the charge carrier mobility therein, i.e., the electron mobility or the hole mobility, may be increased, thereby also resulting in an increased drive current capability. For example, for a standard crystallographic configuration of the silicon material, i.e., a (100) surface orientation with the channel length direction orientated along a <110> crystal axis, tensile strain along the transistor length direction may result in increased electron mobility, while a compressive strain along the transistor length direction may result in an increase of hole mobility. Consequently, a plurality of process technologies have been developed to locally provide a desired type of strain in order to individually enhance transistor performance.
One efficient approach is frequently used and involves the positioning of highly stressed dielectric materials in the vicinity of the channel region after completion of the basic transistor structure. For instance, a portion of the interlayer dielectric material, for instance, an etch stop layer to pattern contact openings in the interlayer dielectric material, may be positioned close to the transistor structure and may therefore act as a source for mechanical stress that may be transferred into the channel region to create the desired type of strain therein. The type and the magnitude of the internal stress level of the dielectric material may be controlled by the deposition parameters wherein, for instance, silicon nitride may be efficiently deposited on the basis of plasma-enhanced deposition techniques with high internal compressive and tensile stress. Although provision of stressed dielectric materials above the individual transistor elements provides significant performance enhancement, the overall efficiency of the strain-inducing mechanism may be determined by the amount of the dielectric material positioned close to the channel region and the internal stress level thereof. It turns out, however, that the magnitude of the internal stress level and the amount of material that may be deposited may significantly depend on the deposition characteristics of the deposition technique under consideration, wherein, in particular for sophisticated device geometries, restrictive deposition-related constraints may be imposed, thereby limiting the efficiency of the strain-inducing mechanism. For example, the pronounced surface topography obtained in highly-scaled transistor elements may be determined by the reduced distance between neighboring circuit elements and the height of the gate electrode structures, which may be substantially determined by the ion-blocking effect during the definition of the drain and source regions. Consequently, although efficient process techniques may be available for enhancing transistor performance, for instance by reducing the gate resistance, increasing the capacitive-coupling, enhancing the charge carrier mobility in the channel region, it turns out that conventional process techniques may not be compatible with significantly enhancing the effect of one or more of these mechanisms, without contributing to a degradation in performance with respect to one or more of the other mechanisms.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.